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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a admc(f)340 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dashdsp 64-lead flash and rom m emory mixed-signal dsp with enhanced analog front end a functional block diagram v ref 2.5v memory block program rom 4k 24 program flash 4k 24 program ram 512 24 data memory 512 16 analog inputs 16-bit three- phase pwm timer serial port sport 0 pio 2 16-bit aux pwm watch- dog timer adsp-21xx base architecture data address generators dag 1 dag 2 program sequencer arithmetic units shifter mac alu program memory address data memory address program memory data data memory data sport 1 motor control peripherals adc subsystem sha 3 10 timers 6 por i sense amp and trip 2 25 7 target applications refrigerator and air conditioner compressors, washing machines industrial variable speed drives, hvac motor types permanent magnet synchronous motors (pmsm), brushless dc motors (bdcm), ac induction motors (acim), switched reluctance motors (srm) features 20 mhz fixed-point dsp core single cycle instruction execution (50 ns) adsp-21xx family code compatibility independent computational units alu multiplier/accumulator barrel shifter multifunction instructions single cycle context switch powerful program sequencer zero overhead looping conditional instruction execution 2 independent data address generators dashdsp is a registered trademark of analog devices, inc. memory configuration 5 12 16-bit data memory ram 512 24-bit program memory ram 4k 2 4-bit program memory rom 4k 24-bit total program flash memory (admcf340 only) 3 independent flash memory sectors 3584 24 bit, 256 24 bit, 256 24 bit low cost pin compatible rom option 16-bit watchdog timer programmable 16-bit internal timer with prescaler 2 double buffered serial ports with spi mode support integrated power-on reset function 3-phase 16-bit pwm generation unit 16-bit center-based pwm generator programmable pwm pulsewidth edge resolution of 50 ns programmable narrow pulse deletion 153 hz minimum switching frequency double/single update mode control individual enable and disable for each pwm output high frequency chopping mode for transformer-coupled gate drives (continued on page 8)
rev. a e2e admc(f)340 (v dd = 5%, gnd = 0 v. for admcf340, t a = e40 c to +85 c. for admc340, t a = e40 c to +125 c. clkin = 10 mhz, unless otherwise noted.) analog-to-digital converter parameter min typ max unit conditions/comments signal input 0.3 3.5 v vaux0, vaux1, vaux2 resolution 1 12 bits linearity error 2 3 4 bits zero offset 3 e32 0 +7 mv comparator delay 600 ns adc high level input current 2 10 = = ()== + =+ =+ =+ () () + =+ ? + + =+ = =+ =
rev. a e3e admc(f)340 voltage reference parameter min typ max unit conditions/comments voltage level (v ref )2 .44 2.50 2.55 v e40 + () + () = = = = = = = = = = () =() () =( ) () =() () =( ) pwmsr . 2 prt0prt, prt0prt1, , , , , , . t . i , reset. i , pwmtrip , prt0prt, prt0prt1. t , t1, rs0, ts0, s1. . s .
rev. a e4e admc(f)340 clkin clkout t ckl t ckil t ckh t ckih t ckin t ckoh figure 1. clock signals timing parameters parameter min max unit clock signals signal t ck is defined as 0.5 t ckin . the admc(f)340 uses an input clock with a frequency equal to half the instruction rate; a 10 mhz input clock (which is equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 mhz). when t ck values are within the range of 0.5 t ckin period, they should be substituted for all relevant timing parameters to obtain specification value as in the following example: t t ns ns ns ns ckh ck =?=?= timing requirements: t ckin clkin period 100 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristics: t ckl clkout width low 0.5 t ck ?10 ns t ckh clkout width high 0.5 t ck ?10 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement: t rsp reset w t pwm s s timing requirement: t pwmtpw pwmtrip w t . s .
rev. a e5e admc(f)340 parameter min max unit serial ports timing requirements: t sck sclk period 100 ns t scs dr/tfs/rfs setup before sclk low 15 ns t sch dr/tfs/rfs hold after sclk low 20 ns t scp sclk in width 40 ns switching characteristics : t cc clkout high to sclk out 0.25 t ck 0.25 t ck + 20 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 30 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 30 ns t scdh dt hold after sclk high 0 ns t scdd sclk high to dt disable 30 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 25 ns t rdv rfs (multichannel, frame delay zero) to dt valid 30 ns specifications subject to change without notice. t cc t cc t scs t rd t rh t scdv t scde t scdd t tdv t rdv clkout sclk dr rfs in tfs in rfs out tfs out dt tfs (alternate frame mode) rfs (multichannel mode, frame delay 0 [mfd = 0]) t scp t sck t scp t sch t scdh t tde figure 2. serial port timing timing parameters
rev. a admc(f)340 e6e absolute maximum ratings * supply voltage (v dd ) . . . . . . . . . . . . . . . . . . e0.3 v to +7.0 v supply voltage (av dd ) . . . . . . . . . . . . . . . . . e0.3 v to +7.0 v input voltage . . . . . . . . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . e0.3 v to v dd + 0.3 v admc340 operating temperature range (ambient) . . . . . . . . . . . . . . . . . . . . e40 + + + () () () () reset p p p et p p10 m0 p11 p12 1 t i p p p0r0 p p2 p1t0 p1 p0 p2rs0 0 1 2 ist 2 1 0 i sese1 1 i sese2 2 i sese pwmtrip 2 1 0 0 1 2 p1 p1 p1 p0t p1pwms 2 pwmsr 2 pr1 p1t1 ps1s0 pwmp pts0 2 2 2 2 0 1 2 2 2 2 22 21 20 1 1 1 reriie t i p p m r r m0st 0 + () () +
rev. a admc(f)340 e7e pin pin no. mnemonic type 1 agnd gnd 2 dgnd1 gnd 3 reset i p i t p i p i t p i 10 p10 i 11 t 12 p11 i 1 p12 i 1 t 1 1 1 1 t 1 p1 i 20 p1 i 21 t 22 p1 i 2 p0t) i 2 p1pwms) i 2 2sp 2 pwmsr i 2 2 2 pr1 i 2 p1t1) i 0 ps1s0) i 1 pwmp i 2 pts0 i p p . m t p2rs0 i p0 i p1 i p1t0 i p2 i p i 0 p0r0 i 1 p i 2 p i i i t t 1sp sp pwmtrip i 0 i 1 i sese i 2 2 i i sese2 i 1 i i sese1 i i 0 i i 1 i 0 i 1 2 i 2 i ist t pi ti esriptis p prt p prt.
rev. a admc(f)340 e8e pm rom 4k 24 pm ram 512 24 bus exchange companding circuitry data address generator no. 2 data address generator no. 1 14 14 24 16 6 dm ram 512 16 r bus 16 dma bus pma bus dmd bus pmd bus instruction register input regs output regs shifter control logic serial port receive reg transmit reg timer input regs output regs mac input regs output regs alu program sequencer flash program memory 4k 24 figure 3. dsp core block diagram general description the admc(f)340 is a low cost, single-chip dsp-based controller suitable for permanent magnet synchronous, ac induction, switched reluctance, and brushless dc motors. the admc(f)340 integrates a 20 mhz, fixed-point dsp core with a complete set of motor control and system peripherals for fast, efficient development of motor controllers. the dsp core of the admc(f)340 is completely code compat ible with the adsp-21xx dsp family and combines three computa- tional units, data address genera tors, and a program sequencer. the computational units comprise an alu, a multiplier/accumu- lator (mac), and a barrel shifter. there are special instructions for bit manipulation, multiplication (x squared), biased rounding, and global interrupt m asking. the system peripherals are the power-on reset circuit (por), the watchdog timer, and two synchronous serial ports. the serial ports are configurable and double buffered, with hardware support for uart, sci, and spi port emulation. the admc(f)340 provides 512 () ( ) () ()() () pwmtrip p rmmp pwmpp i i ip pi i mi ir pwm ip i i pwmt p pm imm
rev. a admc(f)340 e9e dsp core architecture overview figure 3 is an overall block diagram of the dsp core of the admc(f)340. the flexible architecture and comprehensive instruction set allow the processor to perform multiple opera tions in parallel. in one processor cycle (50 ns with a 10 mhz clkin), the dsp core can: ? ? ? ? ? ? ? ? ? ? ? () () () () () () () () () ? () ? () ? () ? () ? () () () () ( ) () () () () () () ()() adsp-2100 family user? manual , third edition, with particular reference to the adsp-2171. serial ports the admc(f)340 incorporates two synchronous serial ports ( sport1 and sport0) for serial communication and multi- processor communication. sport1 is primarily intended for the interfacing of the debugging tools and/or code booting from an external serial memory. the following is a brief list of capabilities of the admc(f)340 sports: ? ? ? ? () ? ?
rev. a admc(f)340 e10e ? ( ) ? () ? ? () pwmsr 1i pwm s r m reset 1i p r i sprt1 1 2 i s p 1 p t11, r1) sprt0 1 i s p 0 p t0, r0, rs0, ts0, s1 s0 2 ) t 1 1 1 i p i, t 2 i e q p prt0prt 1 i i p p prt0prt1 1 i i p p 01 1 2 pwm pwm pwmtrip 1i pwm t s 1 i i sese i i sese1 i sese i i 0 i i ist 1 s i p s i p s i tes 1 m , prtseet prtt r. 2 s1s0 , metr r . iterrpt eriew t m)0 , sp 2 . t sp sprt1 irq0 ) irq1 ), sprt0 , , . t 2 i pwm pwms pwmtrip ). sp irq2 . t . m)0 i , . memr mp t m)0 . i , , . t m)0 rm, rm, s. t 02000. t t ii iii, . t ii. p m m m r t 000000002 rm i t 0000001 rm p m 0020000 r 000001 rm r p m 010001 r 02000020 s p m s 0 02100021 s p m s 1 0220002 s p m s 2 00000 r t iii. m m m r t 0000001 r 02000020 m m r 021000 r 0000 rm m 0000 rm r 0000 m m r
rev. a admc(f)340 e11e flash memory subsystem the admc(f)340 has 4k ()() () () () admcf34x dsp motor controller developers?reference manual for an example. boot-from-flash code a security feature is available in the form of a code that when set causes the processor to execute the program in flash memory at power-up or reset. in this mode, the flash programming u tility and debugger are unable to communicate with the admc(f)340. consequently, the contents of the flash memory can be neither programmed nor read. the boot-from-flash code may be set via the flash programming utility when the user? program is thoroughly tested and loaded into flash program memory at address 0x2200. the user? pro- gram must contain a mechanism for clearing the boot-from-flash code if reprogramming the flash memory is desired. the only way to clear boot-from-flash is from within the user program, by calling the flash_init or auto_erase_reg routines that are included in the rom. the user program must be signaled in some way to call the necessary routine to clear the boot-from-flash code. an example would be to detect a high level on a pio pin during startup initialization and then call the flash_init or auto-erase-reg routine. the flash_init routine will erase the entire user program in flash memory before clearing the boot-from-flash code, thus ensuring the security of the user program. if security is not a c onc er n, th e auto_erase_reg routine can be used to clear the boot-from-flash code while leaving the user program intact. r efer to the admcf34x dsp motor controller developers refer ence manual for further instructions and an example of using the boot-from-flash code. flash program boot sequence on power-up or reset, the processor begins instruction execu tion at address 0x0800 of internal program rom. the rom monitor program that is located there checks the boot-from-flash code. if that code is set, the processor jumps to location 0x2200 in ex ternal flash program memory, where it expects to find the user? appli cation program. if the boot-from-flash code is not set, the monitor attempts to b oot from an external device as described in the admcf34x dsp motor controller developers?reference manual. system interface f igure 4 shows a basic system configuration for the admc(f)340 with an external crystal. admc(f)340 xtal clkin 10mhz clkout reset 22 22 s s tm0tt i i tt ti m0i ttm0 10m0 20m t m0 2t it 2 t
rev. a admc(f)340 e12e reset the admc(f)340 dsp core and peripherals must be correctly reset when the device is powered up to ensure proper unitiza tion. the admc(f)340 contains an integrated power-on-reset (por) circuit that provides a complete system reset on power-up and power-down. the por circuit monitors the voltage on the admc(f)340 v dd pin and holds the dsp core and peripherals in reset while v dd is less than the threshold voltage level, v rst . when this voltage is exceeded, the adm c(f)340 is held in reset for an additional 2 16 dsp clock cycles (t rst in figure 5). during this time (t rst ), the supply voltage must reach the recom mended operating condition. on power-down, when the voltage on the v dd p in falls below v rst ev hyst , the admc(f)340 will be reset. also, if the external reset , m)0 . rst reset rst st t rst pr tm0 msttr sp reset . t reset , rsp . , sp pm rm 0000. sp r t sp , sst, m 0). sprt1 10. sprt0 sprt1 11 12. t sp , memwit, m 0e). t 0. m)0, 0000. t . t sst memwit r m)0 0. treepse pwm trer t pwm m)0 , , pwm im) pmsm). i , pwm pwm em), m), srm). t pwm , , ) , , ). t , , pwm , , pwmtm, pwmt, pwmp r. i , pwm, pwm, pwm) pwm . pwmtrip r pwmswt0 er rret trip pwmstwtrer pwmtrip i sese pwmse0 tpt tr it te rie it pwmte reisters pwmirti reisters titerrpt trer treepse pwmtimi it reset s s pwms t pwmte0 pwmtm10 pwmt0 pwmp0 pwmswt0 metr pwm10 pwm10 pwm10 i sese2 i sese1 pwmm0
rev. a admc(f)340 e13e each of the six pwm output signals can be enabled or disabled by separate output enable bits of the pwmseg register. in addition, three control bits of the pwmseg register permit crossover of the two signals of a pwm. in crossover mode, the high side pwm signals are diverted to the complementary low side output and low side signals are diverted to the corresponding high side output. in many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. in general, there are two common isolation t echniques: optical isolation using optocouplers and trans former isolation using pulse transformers. the pwm controller of the admc(f)340 permits mixing the output pwm signals with a high frequency chopping signal to permit an easy interface to such pulse transformers. the features of this gate-drive chopping mode can be controlled by the pwmgate register. there is an 8-bit value within the pwmgate register that directly controls the chopping frequency. in addition, high frequency chop ping can be inde pendently enabled for the high side and the low side outputs using separate control bits in the pwmgate register. the pwm generator is capable of operating in two distinct modes: single update mode or double update mode. in single update mode, the duty cycle values are programmable only once per pwm period, so that the resultant pwm patterns are symmetrical about the midpoint of the pwm period. in the double update mode, a second updating of the pwm duty cycle values is im plemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower h armonic distortion in three-phase pwm inverters. this tech nique also permits the closed-loop controller to change the average voltage applied to the machine winding at a faster rate, all owing wider closed-loop bandwidths to be achieved. the operating mode of the pwm block (single or double update m ode) is selected by a control bit in modectrl register. the pwm generator of the admc(f)340 also provides an internal signal that synchronizes the pwm switching frequency to the a/d operation. in single update mode, a pwmsync pulse is pro duced at the start of each pwm period. in double update mode, an additional pwmsync pulse is produced at the midpoint of each pwm period. the width of the pwmsync pulse is programmable through the pwmsyncwt register. th e pwm signals produced by the admc(f)340 can be shut off in a number of different ways. first, there is a dedicated asyn chronous pwm shutdown pin, pwmtrip , , , pwm . i , pwm i sese ). , pwm , pwm sp . t pwm pwmswt r . s pwm m)0 ssstt r. i , pwmtrip , pwm . pwm . t pwm ? ? ? ? ( pwmtrip , , pwmswt r) reset t . ? ( ) ( ) ( ) t ck = 1/ f clkout , where f clkout is the clk out f requency (dsp instruction rate). therefore, for a 20 mhz clkout, the fundamental time increment is 50 ns. the value written to the pwmtm register is effectively the n umber of t ck clock increments in half of a pwm period. the required pwmtm value is a function of the desired pwm sw itching frequency ( f pwm ) and is given by: pwmtm f f f f clkout pwm clkin pwm = = pwm switching period, t s , can be written as: t pwmtm t sck =
rev. a admc(f)340 e14e for example, for a 20 mhz clkout and a desired pwm switching frequency of 10 khz (t s = 100 ) pwmtm register is: pwmtm x e = == = fhz pwm ,min , = = () () t d , is related to the value in the pwmdt register by: t pwmdt t pwmdt f dck clkout == pwmdt value of 0x00a (= 10) introduces a 1 () () () (=) tt s dck max = = = ? sec () ( ) ( ) ( ) ( ) ( ) () pwmsyncwt register. the width of the pwmsync pulse, t pwmsync , is given by: tt pwmsyncwt pwmsync ck = + ()
rev. a admc(f)340 e15e which means that the width of the pulse is programmable from t ck to 256 t ck (corresponding to 50 ns to 12.8 ) (=) () () ? + () ? ( ) tp wmcha pwmdt t tp wmtm pwmcha pwmdt t ah ck al ck = = () ( ) d t t pwmcha pwmdt pwmtm d t t pwmtm pwmcha pwmdt pwmtm ah ah s al al s == == t ah and t al are not permitted because the minimum permissible value is zero, corresponding to a 0% duty cycle. in a similar fashion, the maximum value is t s , corresponding to a 100% duty cycle. the output signals from the timing unit for operation in double update mode are shown in figure 8. this illustrates a com pletely general case where the switching frequency, dead time, and duty cycle are all changed in the second half of the pwm period. of course, the same value for any or all of these quantities could be used in both halves of the pwm cycle. however, it can be seen that there is no guarantee that symmetrical pwm signals will be produced by the timing unit in this double update mode. additionally, it is seen that the dead time is inserted into the pwm signals in the same way as in the single update mode. pwmcha 2 2 pwmdt 1 2 pwmdt 2 pwmsyncwt 2 + 1 pwmcha 1 pwmtm 1 pwmtm 2 pwmsyncwt 1 + 1 ah al pwmsync sysstat (3) figure 8. typical pwm outputs of three-phase timing unit in double update mode
rev. a admc(f)340 e16e in general, the on-times of the pwm signals in double update mode are detned by: t ah = ( pwmcha 1 + pwmcha 2 ? pwmdt 1 ? pwmdt 2 ) t ck t al = ( pwmtm 1 + pwmtm 2 ? pwmcha 1 ? pwmcha 2 pwmdt 1 ? pwmdt 2 ) t ck because of the completely general case in double update mode, the switching period is given by: t pwnmtm pwmtm t sck =+ () t ah and t al are constrained to lie between zero and t s . pwm signals similar to those illustrated in figures 7 and 8 can be produced on the bh, bl, ch, and cl outputs by program- ming the pwmchb and pwmchc registers in a manner identical to that described for pwmcha. the pwm controller does not produce any pwm outputs until all of the pwmtm, pwmcha, pwmchb, and pwmchc registers have been written to at least once. after these registers have been written to, the counters in the three-phase timing unit are enabled. writing to these registers also starts the main pwm timer. if, during initialization, the pwmtm register is written to before the pwmcha, pwmchb, and pwmchc registers, the ?st pwmsync pulse (and interrupt if enabled) will be gener- ated (1.5 ) ( ) ( ) ( ) ( ) () () () ( ) d t t pwmcha pwmcha pwmtm pwmtm pwmdt pwmdt pwmtm pwmtm d t t pwmtm pwmtm pwmcha pwmtm pwmtm pwmcha pwmdt pwmdt pwmtm pwmtm ah ah s al al s = = + + ? + + = = ++ () + ++ () +
rev. a admc(f)340 e17e table v. achievable pwm resolution in single and double update modes resolution single update mode double update mode (bit) pwm frequency (khz) pwm frequency (khz) 8 39.1 78.1 9 19.5 39.1 10 9.8 19.5 11 4.9 9.8 12 2.4 4.9 minimum pulsewidth: pwmpd register in many power converter switching applications, it is desirable to eliminate pwm switching pulses shorter than a certain width. it takes a finite time to both turn on and turn off modern power semiconductor devices. therefore, if the width of any of the pwm pulses is shorter than some minimum value, it may be desirable to completely eliminate the pwm switching for that particular cycle. the allowable minimum on-time for any of the six pwm outputs for half a pwm period that can be produced by the pwm con troller may be programmed using the pwmpd register. t he minimum on-time is programmed in increments of t ck so that the minimum on-time produced for any half pwm period, t min , is related to the value in the pwmpd register by: t pwmpd t min ck = pwmpd value of 0x002 defines a permissible minimum on-time of 100 ns for a 20 mhz clkout. in each half cycle of the pwm, the timing unit checks the on-time of each of the six pwm signals. if any of the times are found to be less than the value specified by the pwmpd register, the corre- spond ing pwm signal is turned off for the entire half period, and its complementary signal is turned completely on. consider the example where pwmtm = 200, pwmcha = 5, pwmdt = 3, and pwmpd = 10 with a clkout of 20 mhz, while operating in single update mode. for this case, the pwm switching frequency is 50 khz and the dead time is 300 ns. the minimum permissible on-time of any pwm signal over one-half of any period is 500 ns. clearly, for this example, the dead time adjusted on-time of the ah signal for one-half a pwm period is (5 ?3) = () () () () (=) ( ) = () ()
rev. a admc(f)340 e18e pwmcha = pwmchb pwmtm pwmtm ah al bh bl 2 pwmdt 2 pwmdt ch cl figure 9. an example of pwm signals suitable for ecm control. pwmcha = pwmchb, bh/bl are a crossover pair. al, bh, ch, and cl outputs are disabled. operation is in single update mode. gate drive unit: pwmgate register the gate drive unit of the pwm controller adds features that simplify the design of isolated gate drive circuits for pwm invert- ers. if a transformer-coupled power device gate drive amplifier is used, the active pwm signal must be chopped at a high fre quency. the pwmgate register allows the programming of this high frequency chopping mode. the chopped active pwm signals may be required for the high side drivers only, for the low side drivers only, or for both the high side and low side switches. therefore, independent control of this mode for both high side and low side switches is included with two separate control bits in the pwmgate register. typical pwm output signals with high frequency chopping enabled on both high side and low side signals are shown in figure 10. chopping of the high side pwm outputs (ah, bh, and ch) is enabled by setting bit 8 of the pwmgate regis ter. chopping of the low side pwm outputs (al, bl, and cl) is enabled by setting bit 9 of the pwmgate register. the high chopping frequency is controlled by the 8-bit word (gdclk) written to bits 0 to 7 of the pwmgate register. the period and the frequency of this high frequency carrier are: t gdclk t f f gdclk chop ck chop clkout = + () [] = + () [] gdclk value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 19.5 khz to 5 mhz for a 20 mhz clkout rate. the gate drive features must be programmed before operation of the pwm controller and typically are not changed during normal operation of the pwm controller. following a reset, by default, all bits of the pwmgate register are cleared so that high frequency chopping is disabled. pwmcha pwmcha pwmtm [4 (gdclk + 1) t ck ] pwmtm 2 pwmdt 2 pwmdt figure 10. typical pwm signals with high frequency gate chopping enabled on both high side and low side switches. (gdclk is the integer equivalent of the value in bits 0 to 7 of the pwmgate register.) pwm polarity control, pwmpol pin the polarity of the pwm signals produced at the output pins ah to cl may be selected in hardware by the pwmpol pin. connecting the pwmpol pin to dgnd selects active low pwm outputs, such that a low level is interpreted as a command to turn on the associated power device. conversely, connecting the pwmpol pin to v dd selects active high pwm and the associated power devices are turned on by a high level at the pwm outputs. there is an internal pull-up on the pwmpol pin, so that if this pin becomes d isconnected (or is not co n nected), active hi pwm will be produced. the level on the pwmpol pin may be read from bit 2 of the sysstat register, where a zero indicates a measured low level at the pwmpol pin.
rev. a admc(f)340 e19e switched reluctance mode the pwm block of the admc(f)340 contains a switched reluctance (sr) mode that is controlled by the pwmsr . t pwmsr . i sr , pwm , . t pw m . , pwm . t , . t, , . t pwm sr . i , , ) . t sr pwmsr . t . t pwmsr , sr . , sr pwmsr . pwm s i , pwm . t m)0. , pwmtrip , sp ) pwm . t pwm , pwms , pwmtrip . t pwmtrip , pwm . t pwmtrip 0 ssstt r. t i sese m)0. w i sese ), pw mtrip . t pwmtrip pwmtrip . i , pwm 1 pwmswt r 0201). w pwm pwmtrip i sese . pwm , pwmswt r. r . r pwm pwm. pwmtrip . , pwm pwmtm, pwm, pwm, pwm. pwm r , , pwms. pwm r t pwm r 22. t pwm t i. eriew t m)0 . t , . t m)0 . r 11 . t 1, 2, ) . 1 . e 2.) , . t 1 . t i . re ) .
rev. a admc(f)340 e20e iconst_trim reg <2:0> adc1 adc2 adc3 adc aux comp v1 v2 v3 v ref vaux3 (v) vaux0 vaux0 (v) vaux1 vaux1 (v) vaux2 vaux2 (v) vaux4 vaux4 (v) vaux5 vaux5 (v) vaux6 vaux6 (v) vaux7 vaux7 (v) iconst current voltage current voltage current voltage 8-1 multiplexer modectrl reg <0..1> comp comp comp iconst filter v1 v2 v3 vaux pwmsync (convst) modectrl reg <07> clk capacitor reset capacitor external charging 12-bit adc timer block adc registers pwmtrip e1 e2 e metrre 01011 11 ss t 12t12 tt vict c = () v c = 0 at t = 0. this reset and the start of the conversion process are initiated by the pwmsync pulse, as shown in figure 12. the width of the pwmsync pulse is controlled by the pwmsyncwt register and should be programmed according to figure 12 to ensure complete reset ting. in order to compensate for ic process manufacturing tolerances (and to adjust for capacitor tolerances), the current source of the admc(f)340 is software programmable. the software setting of the magnitude of the iconst current generator is accomplished by selecting one of eight steps over approximately 20% current range. table vi. adc auxiliary channel selection modectrl(5) modectrl(1) modectrl(0) select adcmux adcmux1 adcmux0 vaux0 0 0 0 vaux1 0 0 1 vaux2 0 1 0 vaux3 calibration (v ref )0 1 1 vaux4 1 0 0 vaux5 1 0 1 vaux6 1 1 0 vaux7 1 1 1 table vii. port a multiplexing porta pin first alternate function (peripheral) second alternate function (peripheral) porta8 aux0 (auxiliary pwm output) clkout (system clock) porta7 aux1 (auxiliary pwm output) pwmsync (pwm) porta6 dr1 (data receive sport1) none porta5 fl1 (flag out sport1) dt1 (data transmit sport1) porta4 sclk1 (serial clock sport1) sclk0 (serial clock sport0) porta3 tfs0 (transmit frame sync sport0) none porta2 rfs0 (receive frame sync sport0) none porta1 dt0 (data transmit sport0) none porta0 dr0 (data receive sport0) none
rev. a admc(f)340 e21e v c v1 pwmsync comparator output v cmax t vil t pwm e t crst t crst v vil t figure 12. analog input block operation the adc system consists of four comparators and a single timer that may be clocked at either the dsp rate or half the dsp rate, depending on the setting of the adccnt bit (bit 7) of the modectrl register. when this bit is cleared, the timer counts at a slower rate of clkin. w hen this bit is set, the tim er counts at clkout or twice the rate of clkin. adc1, adc2, adc3, and adcaux are the registers that capture the conversion times, which are the timer values when the associated comparator trips. 100 10 1 1 10 100 c nom e nf tuned i const default i const figure 13. timing capacitor selection adc resolution the adc is intrinsically linked to the pwm block through the p wmsync pulse controlling the adc conversion process. because of this link, the effective resolution of the adc is a function of both the pwm switching frequency and the rate at w hich the adc counter timer is clocked. for a clkout period of t ck and a pwm period of t pwm , the maximum count of the adc is given by: max count t t t for modectrl bit max count t t t for modectrl bit pwm crst ck pwm crst ck =? () () = =? () () = t pwm is equal to the pwm period if operating in single update mode, or it is equal to half that period if operating in double update mode. for an assumed clkout frequency of 20 mhz and pwmsync pulsewidth of 2.0 []= []= () () () () () ( ) () () ( pwmtrip iter triprei triprew 1 e
rev. a admc(f)340 e22e analog front end the main analog inputs of the admc (f) 340 (i sense1 through i sense3 ) are connected to the adc converter through three front end blocks. figure 14 shows the block diagram of a single analog front end. e ach analog front end has two analog inputs: voltage and current. a 2-to-1 multiplexer selects which input will be converted; the multiplexer selection is determined by the modectrl register. the current input (i sense ) is amplified t hrough a bi polar amplifier (gain e2.5). there is an output offset that matches the amplifier o utput signal range to the input signal range of the a/d converter. the amplifier has a built-in overcurrent and open circuit protec tion. the overcurrent protection shuts down the pwm block when the voltage at any of the i sense pins exceeds the trip threshold (high or low). the open circuit protection shuts down the pwm block when any of the i sense inputs is in high impedance (for example the current sense resistor or the current transducer is disconnected). the shut-down signals generated by the amplifiers are then or-ed and filtered in order to avoid spurious trip caused by the switching of the power devices. the amplifier is followed by a sample-and-hold am plifier (sha). the sha time is user- programmable through the sha timer register. the sampling time is set as a delay from the rising edge of the pwmsync signal and is calculated as: t sha cnt t sample ck =+ () ( ) ( ()) () ( ) +(()()) + (()) + () + +(()) ( ) +() (()()) + + + + + = = + +
rev. a admc(f)340 e23e auxiliary pwm timers overview the admc(f)340 provides two variable frequency, variable duty cycle, 16-bit, auxiliary pwm outputs that are available at the aux1 and aux0 pins. when enabled, these auxiliary pwm outputs can be used to provide switching signals to other circuits in a typical motor control system such as power factor corrected front-end converters or other switching power converters. alterna- tively, by adding a suitable filter network, the auxiliary pwm output signals can be used as simple single-bit digital-to-analog converters, which is shown in figure 16. the auxiliary pwm system of the admc(f)340 can operate in two different modes: independent mode or offset mode. the operating mode of the auxiliary pwm system is controlled by bit 8 of the modectrl register. setting bit 8 of the modectrl register places the auxiliary pwm system in the independent mode. in this mode, the two au xiliary pwm generators are completely i ndepen dent and separate switching frequencies and duty cycles may be pro grammed for each auxiliary pwm output. in this mode, the 16-bit auxtm0 register sets the switching frequency of the signal at the aux0 output pin. similarly, the 16-bit auxtm1 register sets the switching frequency of the signal at the aux1 pin. the fundamental time increment for the auxiliary pwm outputs is twice the dsp instruction rate (or 2 t ck ) and the corresponding switching periods are given by: t auxtm t t auxtm t aux ck aux ck 0 1 201 211 = + () = + () a clkout frequency of 20 mhz. the on-time of the two auxiliary pwm signals is programmed by the two 16-bit auxch 0 and auxch 1 registers, according to: t aux auxch t t aux auxch t on, ck on, ck 02 0 12 1 = () = () () t auxtm t offset ck = + () () (== = ) == == ? (+) ? (+) ? ? ? ( ) ()
rev. a admc(f)340 e24e clearing any bit of the data direction register configures the corresponding pio as input while setting the bit configures the pio as output. following a power-on or reset, all bits or porta_dir and portb_dir are cleared, configuring all the pio lines as inputs. the data of the pios is controlled by the data registers (porta_data and portb_data). these registers can be used to read data from those pios configured as input and write data to those configured as outputs. each pio can be individually programmed to be an interrupt source by setting the corresponding bit of the interrupt enable register (porta_inten and portb_inten). to generate an interrupt, the corresponding bit on the data register ( porta_data and portb_data) must change state (high-to-low or low-to-high transition). the transition can be on the corresponding pin (pio configured as input) or by writing into the corresponding bit of the data register (pio configured as output). following a change of state on the data register on a pio configured as interrupt source, the corresponding bit is set in the flag register (porta_flag and portb_flag) and a common pio interrupt is generated. reading the flag register, it is possible to determine which pio has generated the interrupt. reading the flag register automati- cally clears all the bits of the register. following a power-on or reset, all bits of the interrupt enable registers are cleared (no interrupt enabled). each pio line has an internal pull-down resistor so that following a power-on or reset all the pio lines will be read as logic lows if left unconnected. once a pin has been selected as pio function, it can be set as input, output, and interrupt source (either configured as input or output). pio registers the configuration of all registers of the pio system is shown at the end of the data sheet. interrupt control the admc(f)340 can respond to 34 different interrupt sources with minimal overhead. seven of these interrupts are internal dsp core interrupts and 27 are from the on-chip peripherals. the seven dsp core interrupts are sport0 receive and transmit, sport1 receive (or irq0 ) and transmit (or irq1), the internal timer, and two software interrupts. the motor con trol inter rupts are the 25 pios and two from the pwm block (pwmsync pulse and pwmtrip ). sp i rq2 . t . t m)0 t . t . t pwms pwms . t pwmtrip pwmtrip . pi ) pi . t m)0 i, ims, it r sp irq r pwms 0 1 2 tm0 1) 2 tm0 1) 2 1 2 0 2 tm1 1) 1. t pwm s t i t ) m wt timer t m)0 sp . t 1 wtimer r. t i . w , sp . i , 1 ssstt r , m)0 . , 1 ssstt r wtimer r. t . , wtimer r. t , wtimer r wtimer ). wtimer, , wtimer . prrmme iit ipttpt t m)0 2 pi) . t prt ) prt 1 ). t prt . prt 1 i . e prt pi prtseet r. 0 prtseet p0 p, 1 p1 . s prtseet r pi. . , prtseet pi . t p 1 prtset r. t p 1 prtseet r . t p p metr r sprt1 m rt). w pi, p rtir prtir).
rev. a admc(f)340 e25e and pwmtrip prt r pi . t . i i s i pwmtrip 0002 p) p i irq2 ) 0000 pwms 0000 pi 0000 s i 1 0001 s i 0 0001 sprt0 t i 00010 sprt0 r i 0001 sprt1 t i irq1) 00020 sprt1 r i irq0) 0002 t 0002 p) i m i ) ims r sp . t . i , irq2 ) ims r . t ims r m)0 2. i t i it r sp sp . t i r 1 sp . 0 i r sp 1 . w 11 12 i . t it r ) irq0 , irq1, irq2 . s 0 it irq0 , . 1 irq1 2 irq2 . i irq2 . s it r . t i it r 2. iterrpt perti , rm m)0 rm 00000 0002. s , isr) . , mp isr. w , ) . i t, sprt0, sprt1, , . , mp isr . m . w , irq r pwms pwmtrip prt r pi , irq2 . t sp irq . i , . r irq r pwmtrip pwms , isr . pi prt r pi . r r prt , isr . t 2. sstem trer t m)0 1. m sp 2. sp irq2 . . e pwmtrip pwms . sprt1 sprt0 . pwm . s . pwm . ssstt) pwmtrip , , pwm 10. p , , sprt1 sprt0 t m)0 sprt0 sp rt1. sprt1 . 1 sprt0 sprt1 . sprt0 . sprt0 sprt, rt, spi. sprt1 t sprt1 rt . t metr r. w sprt1 , sprt1 s1) s1 s0 . t s1 . sprt1 1) 1t1 . t .
rev. a admc(f)340 e26e with sport1 configured in uart mode, the sport0 serial clock (sclk0) is externally available through the sclk1/ sclk0 pin. the sport1 data transmit (dt1) is externally available through the fl1/dt1 pin. sport0 configuration sport0 can be configured in sport, uart, and spi modes. sport0 can be configured for uart mode. in this mode, the dr0 and rfs0 signals of the internal serial port are con nected together. dsp core sport1 dt1 fl1 tfs1 rfs1 dr1 sclk1 dsp core sport0 sclk0 dt0 dr0 tfs0 rfs0 spi control block modectrl register (04) sport1 boot mode/uart mode modectrl register (15) sport0 sport mode/uart mode modectrl register (14..13..12) sport0 spi interface control dt1/fl1 dr1 sclk1/sclk0 dt0 dr0 tfs0 rfs0 admc(f)340 figure 18. sport0 and sport1 internal multiplexing (simplified diagram) sport0 can be configured to operate as a master spi interface. the spi mode is set through bit 14 of the modectrl regis ter. when sport0 is configured as an spi interface, the sport i/o pins assume the configuration shown in table xi (admcf340 only). the slave select pin automatically generates the select signal at each word transfer ( admcf340 only). this pin can also be used as a general-pur pose i/o during the spi transfer without affecting the sport opera tions (admcf340 only). the spi clock polarity and phase are configurable through bits 13 and 12 of the modectrl register (admcf340 only). the spi transfer using clock phase is shown in figure 19 and figure 20 ( admcf340 only).
rev. a admc(f)340 e27e 12345 n see note 1 see note 2 msb msb lsb lsb sck cycle # sck (polarity = 0) sck (polarity = 1) ss mosi miso notes 1. lsb of previously transmitted word 2. undefined figure 19. spi transfer using clock phase cpha = 0 12345 n see note 1 see note 2 msb msb lsb lsb sck cycle # sck (polarity = 0) sck (polarity = 1) ss mosi miso notes 1. lsb of previously transmitted word 2. undefined figure 20. spi transfer using clock phase cpha = 1 table xi. sport0 pin assignment in spi mode sport i/o signal spi mode spi mode i/o dt0 (data transmit) mosi (master output/slave input) output dr0 miso (master input slave output) input tfs0 ss (slave select) output rfs0 unused n/a sclk0 sck (serial clock) output
rev. a admc(f)340 e28e table xii. peripheral register map address (hex) name bits used function 0x2000 adc1 [15 . . . 4] adc results for v1/i sense 1 0x2001 adc2 [15 . . . 4] adc results for v2/i sense 2 0x2002 adc3 [15 . . . 4] adc results for v3/i sense 3 0x2003 adcaux [15 . . . 4] adc results for vaux 0x2004 porta_dir [8 . . . 0] pa8...pa0 pins direction setting 0x2005 porta_data [8 . . . 0] pa8...pa0 pins input/output data 0x2006 porta_inten [8 . . . 0] pa8...pa0 pins interrupt enable 0x2007 porta_flag [8 . . . 0] porta pins interrupt status 0x2008 pwmtm [15 . . . 0] pwm period 0x2009 pwmdt [9 . . . 0] pwm dead time 0x200a pwmpd [9 . . . 0] pwm pulse deletion time 0x200b pwmgate [9 . . . 0] pwm gate drive configuration 0x200c pwmcha [15 . . . 0] pwm channel a pulsewidth 0x200d pwmchb [15 . . . 0] pwm channel b pulsewidth 0x200e pwmchc [15 . . . 0] pwm channel c pulsewidth 0x200f pwmseg [8 . . . 0] pwm segment select 0x2010 auxch0 [7 . . . 0] aux pwm output 0 0x2011 auxch1 [7 . . . 0] aux pwm output 1 0x2012 auxtm0 [7 . . . 0] auxiliary pwm frequency value 0x2013 auxtm1 [7 . . . 0] auxiliary pwm frequency value/offset 0x2014 reserved 0x2015 modectrl [8 . . . 0] mode control register 0x2016 sysstat [3 . . . 0] system status 0x2017 irqflag [1 . . . 0] interrupt status 0x2018 wdtimer [15 . . . 0] watchdog timer 0x2019 . . . 43 reserved 0x2044 portb_dir [15 . . . 0] pb15...pb0 pin direction setting 0x2045 portb_data [15 . . . 0] pb15...pb0 data and mode control 0x2046 portb_inten [15 . . . 0] pb15...pb0 pin interrupt enable 0x2047 portb_flag [15 . . . 0] pb15...pb0 pin interrupt status 0x2048 reserved 0x2049 porta_select [15 . . . 0] pio mode select 0x204a . . . 5f reserved 0x2060 pwmsyncwt [7 . . . 0] pwmsync pulsewidth 0x2061 pwmswt [0] pwm s/w trip bit 0x2062 . . . 67 reserved 0x2068 iconst_trim [2. . .0] iconst_trim 0x2069 sha1_tm [15...0] sample-and-hold timer 0x206a sha2_tm [15...0] sample-and-hold timer 0x206b sha3_tm [15...0] sample-and-hold timer 0x2070 reserved 0x2080 fmcr [15. . .0] flash memory control register 0x2081 fmar [11. . .0] flash memory address register 0x2082 fmdrh [13. . .0] flash memory data register high 0x2083 fmdrl [15. . .0] flash memory data register low 0x2084 . . . ff reserved
rev. a admc(f)340 e29e table xiii. dsp core registers address name bits used function 0x3ffa sport0_rx_words1 [15 . . . 0] multichannel receive word enables 0x3ff9 sport0_rx_words0 [15 . . . 0] multichannel receive word enables 0x3ff8 sport0_tx_words1 [15 . . . 0] multichannel transmit word enables 0x3ff7 sport0_tx_words0 [15 . . . 0] multichannel transmit word enables 0x3ff6 sport0_ctrl_reg [15 . . . 0] control register 0x3ff5 sport0_sclkdiv [15 . . . 0] serial clock divide modulus 0x3ff4 sport0_rfsdiv [15 . . . 0] receive frame sync divide modulus 0x3ff3 sport0_autobuf ctrl [15 . . . 0] autobuffer control register 0x3ff2 sport1_ctrl_reg [15 . . . 0] control register 0x3fff syscntl [15 . . . 0] system control register 0x3ffe memwait [15 . . . 0] memory wait state control register 0x3ffd tperiod [15 . . . 0] interval timer period register 0x3ffc tcount [15 . . . 0] interval timer count register 0x3ffb tscale [7 . . . 0] interval timer scale register 0x3ffa . . . f3 reserved 0x3ff2 sport1_ctrl_reg [15 . . . 0] sport1 control register 0x3ff1 sport1_sclkdiv [15 . . . 0] sport1 clock divide register 0x3ff0 sport1_rfsdiv [15 . . . 0] sport1 receive frame sync divide 0x3fef sport1_autobuf_ctrl [15 . . . 0] sport1 autobuffer control register
rev. a admc(f)340 e30e flash memory control register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x2080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 flash memory address register 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0x2081 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved always read 0 address 11 0 flash memory data register low (fmdrl) 0 0 0 0 0 0 0 00 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved always read 0 0x2083 status 5e0 data 7e0 flash memory data register high (fmdrh) 0 0 0 0 0 0 0 00 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x2082 data 23e8 most significant bit is on the left. for example, data23 is bit 15 of fmdrh. boot-from-flash-code figure 21. contguration of flash memory registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e31e pwmsyncwt + 1 f clkout t pwmsync, on = pwmswt (r/w) 15 14 13 12 11 10 9876543210 000 0 0000 00000000 dm (0x2061) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 00 111 000 00000 pwmsyncwt (r/w) pwmsyncwt dm (0x2060) 15 14 13 12 11 10 9876543210 000 00000 00000000 pwmdt (r/w) pwmdt f clkout 2 pwmtm f pwm = dm (0x2009) pwmtm (r/w) pwmtm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2008) 0 0 0 0 0 0 0 0 0 pwmseg (r/w) 15 14 13 12 11 10 9876543210 0000000 dm (0x200f) 2 pwmtm f clkout t d = seconds ch output disable cl output disable bh output disable bl output disable ah output disable al output disable 0 = enable 1 = disable a channel crossover b channel crossover c channel crossover 0 = no crossover 1 = crossover figure 22. contguration of pwm registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e32e 0 0 0 0 0 0 0 0 0 0 low side gate chopping 0 = disable 1 = enable high side gate chopping dm (0x200b) gdclk gate drive chopping frequency pwmgate (r/w) pwmpd (r/w) dm (0x200a) pwmpd pwmcha (r/w) pwm channel a duty cycle dm (0x200c) pwmchb (r/w) pwm channel b duty cycle dm (0x200d) pwmchc (r/w) dm (0x200e) pwm channel c duty cycle t min = pwmpd f clkout f chop = 4 (gdclk + 1) f clkout 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9876543210 15 14 13 12 11 10 9876543210 0 0 0 0 0 0 0 0 0 0 0 00 0 figure 23. contguration of additional pwm registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e33e porta_dir (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9876543210 pa0epa8 dm (0x2004) 0 = input 1 = output portb_dir (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9876543210 pb0epb15 dm (0x2044) (not used in admcf341) 0 = input 1 = output porta_data (r/w) 0 0 0 0 15 14 13 12 11 10 9876543210 0 0 0 0 pa0epa8 dm (0x2005) 0 = low level 1 = high level 00 000000 portb_data (r/w) 15 14 13 12 11 10 9876543210 pb0epa15 dm (0x2045) (not used in admcf341) 0 = low level 1 = high level 0000000000000000 porta_select (r/w) 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 11 1 1 1 0 = dr0 1 = pa0 0 = dt0 1 = pa1 0 = rfs0 1 = pa2 0 = tfs0 1 = pa3 0 = aux0/clockout 1 = pa8 0 = aux1/pwmsync 1 = pa7 0 = dr1 1 = pa6 0 = sclk1/sclk0 1 = pa4 0 = pwmsync 1 = aux1 0 = dt1/fl1 1 = pa5 0 = clockout 1 = aux0 dm (0x2049) figure 24. contguration of pio registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e34e dm (0x2046) portb_inten (r/w) 15 14 13 12 11 10 98 7654 3210 0 = interrupt disable 1 = interrupt enable (not used in admcf341) 0 000000000000000 dm (0x2007) porta_flag (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = interrupt disable 1 = interrupt enable 00 0 0000000000000 dm (0x2047) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 portb_flag (r/w) 0 = interrupt disable 1 = interrupt enable (not used in admcf341) 0000000000000000 dm (0x2006) porta_inten (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 0000000000000 0 = interrupt disable 1 = interrupt enable figure 25. contguration of additional pio registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown. 0 0 0 0 dm (0x2010) auxch0 (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2011) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2012) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2013) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aux1 period = 2 (auxtm1) t ck offset = 2 (auxtm1) t ck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 t on, aux0 = 2 (auxch0) t ck t on, aux1 = 2 (auxch1) t ck aux0 period = 2 (auxtm0 + 1) t ck auxch1 (r/w) auxtm0 (r/w) auxtm1 (r/w) p figure 26. contguration of auxiliary pwm register default bit values are shown; if no value is shown, the bit teld is undetned at reset.
rev. a admc(f)340 e35e 0 0 0 0 dm (0x2000) adc1 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2001) adc2 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2002) adc3 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2003) adcaux (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2068) iconst_trim (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iconst min = bits 0e2 cleared. iconst max = bits 0e2 set. 0 0 0 00 0 0 00 0 0 00 0 0 0 sha1_tm (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2069) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x206a) sha2 _tm (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x206b) sha3 _tm (r/w) conversion status 0 = data ready 1 = not ready conversion status 0 = data ready 1 = not ready conversion status 0 = data ready 1 = not ready figure 27. contguration of adc registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e36e adc mux control 0 = boot mode 1 = uart mode sport1 mode select 0 = disable 1 = enable pwmsync interrupt 0 = disable 1 = enable pwmtrip i nterrupt 0 0 0 0 0 0 00 0 0 0 sysstat (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = low 1 = high dm (0x2016) 0 = normal 1 = watchdog reset occurred pwmtrip pistts wt stts pwmtimer stts 0 1stpwm e 1 2pwm e 0 0 00 0 0 0 00 0 0 00 0 0 0 metrrw m0201 0siepteme 1epteme 1 1 1 12 11 10 2 1 0 mtr 0 0 00 0 0 0 00 0 0 0 1 1 1 12 11 10 2 1 0 0 0 00 irqr pwmtrip interrupt pwmsync interrupt dm (0x2017) 0 0 0 0 0 0 00 0 0 00 0 0 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdtimer (w) dm (0x2018) 01 0 = no interrupt 1 = interrupt occurred pwm update mode select adc counter 0 = clkin rate 1 = clkout rate aux pwm mode select channel 1 selection 0 = offset mode 1 = independent mode 0 = i sense 1 = voltage channel 2 selection 0 = i sense 1 = voltage channel 3 selection 0 = i sense 1 = voltage sport 0 mode select 0 = sport mode 1 = uart mode sport 0 spi mode 0 = sport 1 = sp1 mode spi clock polarity 0 = standard 1 = reverse spi clock phase 0 = pha0 1 = pha1 adc mux control figure 28. contguration of status/control registers default bit values are shown; if no value is shown, the bit teld is undetned at reset.
rev. a admc(f)340 e37e table xiv. auxiliary analog input selection selection modectrl (5) modectrl (1) modectrl (0) vaux0 (1) 0 0 0 vaux1 (1) 0 0 1 vaux2 (1) 0 1 0 v ref (1) 0 1 1 vaux4 1 0 0 vaux5 1 0 1 vaux6 1 1 0 vaux7 1 1 1
rev. a admc(f)340 e38e sport1 receive or irq0 i iterrptre iterrpter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 timer stwre0 stwre1 irq2 timer stwre0 stwre1 irq2 spreister 1 1 1 12 11 10 2 1 0 sprt1trsmitr irq1 sprt1reeier irq0 sprt1trsmitr irq1 1 1 0 0 0 irq0 sensitivity 0 = level 1 = edge icntl irq1 sensitivity irq2 sensitivity interrupt nesting 0 = disable 1 = enable dsp register 43210 imask (r/w) peripheral (or irq2 ) timer sport1 receive (or irq0 ) sport1 transmit (or irq1 ) software 0 software 1 0 0 0 0 0 0 0 00 0 0 00 1 1 0 dsp register 0 = disable (mask) 1 = enable 0 = disable (mask) 1 = enable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sport0 transmit sport0 receive sport0 receive sport0 transmit sport0 transmit sport0 receive figure 29. contguration of interrupt control registers default bit values are shown; if no value is shown, the bit teld is undetned at reset. reserved bits are shown in a gray teld?t hese bits should always be written as shown.
rev. a admc(f)340 e39e 1 dm (0x3ffe) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 memwait (r/w) 1 1 0 0 0 0 00 0 11 1 1 1 sport1 configure 0 = fi, fo, irq0, irq1, sclk 1 = serial port sport1 enable 0 = disabled 1 = enabled syscntl (r/w) dm (0x3fff) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1111111 11111111 figure 30. contguration of registers default bit values are shown; if no value is shown, the bit teld is undetned at reset.
rev. a ?0 c02723??0/02(a) printed in u.s.a. admc(f)340 64-lead thin plastic quad flatpack [lqfp] (st-64a) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.45 0.37 0.30 0.80 bsc 14.00 bsc sq 1.60 max seating plane 0.75 0.60 0.45 view a 7 0 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 16.00 bsc sq compliant to jedec standards ms-026beb 10 6 2 outline dimensions revision history location page 10/02?ata sheet changed from rev. 0 to rev. a. c hanged admcf340 to admc(f )340 ................................................................................................. ..................... un iversal changes to pr oduct ti tle ....................................................................................................... ................................................1 changes to fe a tures ............................................................................................................ ......................................................1 changes to volt a ge reference ................................................................................................... ..........................................3 changes to absolute maxi mum rati ngs ............................................................................................ ...............................6 changes to orderi ng gui de ...................................................................................................... ..............................................6 changes to sport0 configuration section ........................................................................................ ...........................................26

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